module instDecoder (
    input   logic   [31:0]      Inst_code,
    output  logic   [5:0]       op_code,
    output  logic   [4:0]       rs_addr,
    output  logic   [4:0]       rt_addr,
    output  logic   [4:0]       rd_addr,
    output  logic   [4:0]       shamt,
    output  logic   [5:0]       func,
    output  logic   [15:0]      imm,
    output  logic   [25:0]      address
);


always_comb op_code = Inst_code[31:26];

always_comb begin
    case (op_code)
        6'b000000: begin : R_Type
            rs_addr = Inst_code[25:21];
            rt_addr = Inst_code[20:16];
            rd_addr = Inst_code[15:11];
            shamt   = 5'd0;
            func    = Inst_code[5:0];
            imm     = 16'd0;
            address = 26'd0;
        end
        6'b001000,  // addi
        6'b001100,  // andi
        6'b001110,  // xori
        6'b001011,  // sltiu
        6'b100011,  // lw
        6'b101011,  // sw
        6'b000100,  // beq
        6'b000101:  // bne
        begin : I_Type
            rs_addr = Inst_code[25:21];
            rt_addr = Inst_code[20:16];
            rd_addr = 5'd0;
            shamt   = 5'd0;
            func    = 6'd0;
            imm     = Inst_code[15:0];
            address = 26'd0;
        end
        6'b000010,  // j
        6'b000011:  // jal
        begin : J_Type
            rs_addr = 5'd0;
            rt_addr = 5'd0;
            rd_addr = 5'd0;
            shamt   = 5'd0;
            func    = 6'd0;
            imm     = 16'd0;
            address = Inst_code[25:0];
        end
        default: begin
            rs_addr = 5'd0;
            rt_addr = 5'd0;
            rd_addr = 5'd0;
            shamt   = 5'd0;
            func    = 6'd0;
            imm     = 16'd0;
            address = 26'd0;
        end
    endcase
end

endmodule
